Lightweight ANU-II block cipher on field programmable gate array

Nowadays the number of embedded devices communicating over a network is increasing. Thus, need for security appeared. Considering various constraints limited resources very important. These include power, memory, area and latency. A perfect environment satisfying requirements in lightweight cryptography. recent algorithm that has low high throughput which ANU-II block cipher. Many technologies like internet things (IoT) needed hardware architectures to provide it. In IoT issues size power consumption smaller gate counts take care by using This paper presents data path implementation field programmable array (FPGA). 64-bit Also, this research comparisons based on design metrics among our cipher other existing designs. The result proposed shows 1502.31, 1951.86, 2696.47 Mbps. it efficiency 7.0201, 31.9977, 10.6579 Mbps/slice as compared ciphers paper.